1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device for avoiding latch-up problem.
2. Description of Related Art
Designation of semiconductor devices is currently driven to advance in accordance with higher degree of integration and more complicated requirements of the semiconductor devices. For example, high-voltage devices must be designed for being operated under a high voltage without interfering with other elements. FIG. 1 is exemplified herebelow to illustrate problems and limitations of a conventional high-voltage device.
FIG. 1 is a cross-sectional view of a conventional high-voltage device, for example, a complementary metal-oxide-semiconductor (CMOS) transistor composed of two lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors.
Referring to FIG. 1, the high-voltage device includes P-type substrate 100, gates 102, 104, gate dielectric layers 106, 108, P-well 112p, a P-tub 114P, doped regions 116p, 118p, 120p, N-tubs 122n, 124n, doped regions 126n, 128n, 130n, isolation structure 134, dielectric layer 136, interconnect 138 and dielectric layer 140. The P-type substrate 100 includes a high-voltage N-type metal-oxide-semiconductor (HVNMOS) transistor in an area marked as HVNMOS, and a high-voltage P-type metal-oxide-semiconductor (HVPMOS) transistor in an area marked as HVPMOS. The doped regions 126n, 128n and the gate 102 serve as source, drain and gate of the HVNMOS transistor respectively, and the doped regions 120p, 118p and gate 104 serve as source, drain, and gate of the HVPMOS transistor respectively. The doped regions 116p, 118p and 120p are of p+ conductive type, and the doped regions 126n, 128n and 130n are of n+ conductive type.
The conventional high-voltage device shown in FIG. 1 has following disadvantages:
1. Such a high-voltage device is likely have a latch-up problem. The doped region 120p, the N-tub 124n and the P-type substrate 100 serve respectively as an emitter, a base and a collector that constitute a parasitic bipolar transistor, and doped regions 126n, P-type substrate 100 and N-tub 124n serve respectively as an emitter, a base and a collector that constitute another parasitic bipolar transistor. As such, when a product of current gains of these two double carrier transistors is greater than 1, the high-voltage device is incapable of operating normally.
2. The aforementioned HVPMOS transistor and HVNMOS transistor are disposed on a P-type substrate 100. Therefore, input voltage applied on the doped region 120p is directly applied on the P-type substrate 100. Accordingly, input voltage of the device is very much restricted, thus limiting operation range of such high-voltage devices.
3. Generally, there are often some other semiconductor elements disposed on the P-type substrate 100. However, the conventional high-voltage device provides no isolation structure for isolating those other elements from the high-voltage device in order to avoid interference therebetween.
Accordingly, operation of one semiconductor element affects the others on the substrate, and therefore must be improved.